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10.13 I DD and I DDQ Specification Parameters and Test Conditions
10.13.1 I DD and I DDQ Measurement Conditions
In this section, I DD and I DDQ measurement conditions such as test load and patterns are defined.
Figure 105 shows the setup and test load for I DD and I DDQ measurements.
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I DD currents (such as I DD0 , I DD1 , I DD2N , I DD2NT , I DD2P0 , I DD2P1 , I DD2Q , I DD3N , I DD3P , I DD4R , I DD4W ,
I DD5B , I DD6 , I DD6ET and I DD7 ) are measured as time-averaged currents with all V DD balls of the
DDR3 SDRAM under test tied together. Any I DDQ current is not included in I DD currents.
I DDQ currents (such as I DDQ2NT and I DDQ4R ) are measured as time-averaged currents with all
V DDQ balls of the DDR3 SDRAM under test tied together. Any I DD current is not included in I DDQ
currents.
Attention: I DDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM.
They can be used to support correlation of simulated IO power to actual IO power as
outlined in Figure 106. In DRAM module application, IDDQ cannot be measured separately
since V DD and V DDQ are using one merged-power layer in Module PCB.
For IDD and I DDQ measurements, the following definitions apply:
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―0‖ and ―LOW‖ is defined as V IN ≤ V ILAC(max) .
―1‖ and ―HIGH‖ is defined as V IN ≥ V IHAC(min) .
― MID- LEVEL‖ is defined as inputs are V REF = V DD / 2.
Timings used for I DD and I DDQ Measurement-Loop Patterns are provided in Table 38.
Basic I DD and I DDQ Measurement Conditions are described in Table 39.
Detailed I DD and I DDQ Measurement-Loop Patterns are described in Table 40 through Table 47.
I DD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not
limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0 b (Output Buffer enabled in MR1);
Rtt_Nom = RZQ/6 (40 Ohm in MR1);
Rtt_WR = RZQ/2 (120 Ohm in MR2);
Attention: The I DD and I DDQ Measurement-Loop Patterns need to be executed at least one time
before actual I DD or I DDQ measurement is started.
Define D = {CS#, RAS#, CAS#, WE# } := {HIGH, LOW, LOW, LOW}
Define D# = {CS#, RAS#, CAS#, WE# } := {HIGH, HIGH, HIGH, HIGH}
Table 38 – Timings used for IDD and IDDQ Measurement-Loop Patterns
Speed Bin
DDR3-1333
DDR3-1600
DDR3-1866
CL-nRCD-nRP
Part Number Extension
tCK
CL
nRCD
nRC
nRAS
nRP
nFAW
nRRD
nRFC 1 Gb
9-9-9
-15/15I/15A/15K
1.5
9
9
33
24
9
30
5
74
11-11-11
-12/12I/12A/12K
1.25
11
11
39
28
11
32
6
88
13-13-13
-11
1.07
13
13
45
32
13
33
6
103
Unit
nS
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
Publication Release Date: Dec. 09, 2013
Revision A05
- 122 -
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